MIRAGE: MultI-coRe, multi-level, WDM-enAbled embedded optical enGine for TErabit board-to-board and rack-to-rack parallel optics
[October 2012 – May 2016]
PCRL coordinated MIRAGE which was a European project on photonic integration, aiming to implement cost-optimized components for high-speed optical interconnects. In order to raise the bar of interconnect speed and avoid a capacity crunch in the data centre, MIRAGE introduced new concepts providing new degrees of multiplexing. Within the project a manifold of new developments and disciplines were leveraged effectively:
- data transmission in single-mode, multi-core fibre
- introduction of multi-level modulation schemes for capacity upgrade
- introduction of wavelength multiplexing in Active Optical Cables
- introduction of space division multiplexing in multi-core fibers
To introduce these new concepts in the datacom sector in a cost-effective and commercially viable manner, MIRAGE reassessed the existing technological baseline to develop a flexible and upgradeable “optical engine” capable of different configurations in order to adapt the application requirements. The MIRAGE optical engine blends the most prominent optical interconnect technologies (VCSELs, silicon photonics) with concepts new to the datacom sector (multi-core fiber, wavelength multiplexing) using state-of-the-art 2.5 and 3D integration.
Achievement of the project’s technological objectives has led to a significant number of scientific publications in top-tier journals and conferences. The technical competencies developed in MIRAGE have opened up extensive exploitation opportunities to the project partners, enhancing their competitiveness in the multi-billion market of optical interconnects and creating new employment opportunities in Europe.
Summary of project context and objectives
MIRAGE was a collaborative project on photonic integration that brought together eight leading European universities, research centers and companies. The project was launched in October 2012 and was co-funded by the European Commission through the Seventh Framework Programme (FP 7).
MIRAGE aimed to raise the bar in the speed of optical links that are used for interconnecting servers and switches in datacenter networks (optical interconnects). Being the repositories of online content, datacenters are now becoming the “hot spots” of the internet and traffic demand follows double-digit growth, reaching 25% CAGR. With current scaling curves of networking equipment lagging behind this tremendous growth, content providers face up to the challenge of a capacity crunch in the datacenter, failing to deliver data efficiently to the end user.
In order to change the scaling trajectory of optical interconnects, MIRAGE has introduced new multiplexing concepts that provide new dimensions of parallelization in optical interconnects. As a result, in addition to scaling of line rate, MIRAGE leverages the use of more efficient modulation formats capable of pushing through more data with the same bandwidth, as well as wavelength division multiplexing (WDM) and space division multiplexing (SDM) in multicore fibers, enhancing bandwidth density and saving component costs.
MIRAGE developed a flexible “optical engine” that pushes the envelope in all the dimensions used for scaling overall capacity (line rate, efficient modulation, WDM, SDM). The MIRAGE optical engine relies on the most prominent AOC technologies (VCSELs, silicon photonics) combined with state-of-the-art assembly methodologies to reduce the overall BOM and develop value-added components.
The project core technological objectives were:
- develop 3D photonic-electronic silicon platform
- fabricate WDM VCSEL arrays for 40 Gb/s modulation and flip-chip assembly
- develop high-speed linear electronic components (VCSEL drivers, TIAs)
- develop advanced methodology for industry-compatible assembly & packaging on a 2.5D/3D integration platform combining silicon photonics and electronics
- develop low cost techniques for multicore-fiber coupling
- fabricate application-specific components using the developed 2.5D/3D optical engine
- evaluate components in application scenarios
To provide a vehicle for demonstration and evaluation of the developed technology, MIRAGE aimed at three types of prototypes:
- PCB-based, providing a direct evolution path from current commercial products
- 5D Silicon Electrical Carrier based
- 3D Silicon Electro-Optical Carrier based
Main Scientific and technical (S&T) results and foregrounds
The technical work in MIRAGE was organised in 6 work-packages (WPs), for efficient coordination and tracking of the parallel activities towards the project objectives. A dedicated WP for project coordination and management ensured coherence of the work and liaison with the EC. Interaction among the WPs is shown in Figure 1.
The main results per WP are summarized below:
WP2: System design and methodology for integration and packaging processes
Activities in WP2 aim at the exchange of technical information among partners, at defining the system-level specifications of MIRAGE components, at identifying the critical interfaces between individual building blocks and confirming their compatibility, at generating the device models for system-level simulations of MIRAGE systems and at defining the methodology of the integration and packaging procedures. Design activities in WP2 received input from the rest of the WPs in order to refine the specifications of the MIRAGE components in subsequent design cycles.
During the course of the project, WP2 has offered a forum for defining the system specifications of MIRAGE components, devices and systems, for aligning the specifications of MIRAGE components and ensure their compatibility, for defining the integration methodologies taking into account the specific characteristics of the different integration platforms, and for performing simulation studies regarding the system performance of MIRAGE devices and systems. WP2 has also taken care of a smooth transition of all these activities into WP5 at the final stages of the project.
WP3: Optical passives for Multi-lane to multi-core fiber interfaces
WP3 concerns the design of value-added passive components and involves silicon nanophotonic boards as well as laser inscribed glass interposers.
Silicon photonic boards
Designs were generated for vertical grating couplers, polarization-insensitive wavelength demultiplexers and in-plane couplers.
Vertical grating couplers
Grating couplers (GCs) for perfectly vertical coupling schemes facilitating the hybrid integration of single polarization and directly modulated VCSELs-to-SOI substrates have been thoroughly studied and characterized over the course of the project. In order to meet the requirements of rapid prototyping, we have designed solely fully etched GC based on 340 nm thick SOI substrates targeting high coupling efficiency and high immunity to optical back reflections at telecom wavelengths.
Initially, uniform and chirped GC versions for TM polarization have been designed and tested yielding a coupling loss of 7.5 dB and 6.5 dB at 1560nm, respectively. By chirping the period length of the very first scattering units of the GC, second order back reflection was reduced improving the coupling efficiency to the waveguide by 1 dB compared to uniform GC version. In addition, minimum back reflection to the fiber was measured as low as -17 dB. Figure 2 (a) shows a schematic illustration of the fully etched GC while experimental results for the transmitted power to waveguide and the back reflection to the fiber are depicted in Figure 2 (b).
In the second design phase of TM based GCs, a particle-swarm-optimization (PSO) algorithm was employed to break GC’s symmetry in order to minimize the second order back reflection to the waveguide. Simulations predicted a coupling loss of 4.5 dB at 1550 nm with a 1 dB BW of 47 nm and a minimum waveguide back-reflection of -20 dB. During the optimization process the minimum feature size of the apodized GC was restricted to 80-100nm. A schematic view of the apodized GC and simulations results are shown in Figure 3 (a) and (b), respectively. Figure 3 (c) illustrates a cross-sectional SEM image of the fabricated GC. The experimental results for the coupling loss and the measured back reflection to the fiber are shown in Figure 3 (d).
The apodized GC version has been studied and modelled including also the dielectrics employed by the 0.35 cm CMOS Back-End-Of-Line process flow of AMS. Leveraging the presence of the SiN at BEOL process for passivation purposes, we proposed the formation of a simple Anti-Relfection (AR) coating based on SiO2/SiN layers optimizing the GC performance. Unlike other demonstrations where multiple SiO2/SiN have been considered between each metal layer along the BEOL stack, we restricted our designs to the passivation section that lies above the last metal layer keeping the process flow almost unmodified. The feasibly of this concept has been confirmed through numerical simulations.
Figure 4 (a) illustrates the apodized GC and the proposed AR coating on top of the standardized AMS BEOL stack. Simulations have shown a peak coupling loss of 3.5 dB at 1550nm with a minimum back reflection to the VCSEL of -13 dB (see Figure 4(b)).
During the third year of the project, we have designed bi-directional grating couplers for perfectly vertical coupling based on sub-wavelength refractive index engineering compatible with DUV lithography tools (193nm DUV). Bi-directional GCs constitute an attractive approach towards hybrid integration of VCSEL-on-SOI as they offer enhanced alignment tolerance compared to the unidirectional counterparts. Simulation results dictated a coupling efficiency of -0.87 dB at 1548 nm and an ultra-low direct back-reflection of -27.4 dB at 1549 nm for the TE Sub-Wavelength-GC (SWGC). The TM SWGC exhibited a coupling efficiency of -1.47 dB at 1560 nm with a minimum direct back-reflection of -14.2 dB at 1559 nm. For both the TE and TM SWGC the feature sizes are larger than 100 nm complying with the design rules imposed by the DUV lithography. Figure 5 (a) depicts a conceptual schematic of the envisioned 3D integration of a single polarization VCSEL on top of the SWGC. A visual impression of the power coupled to the silicon waveguides through the SWGC is illustrated in Figure 5(b). Simulation results for the TE and TM SWGCs are summarized in Figure 5(c).
Polarization-insensitive wavelength demultiplexers
Polarization drifts during fiber transmission result in a random state-of-polarization entering the MIRAGE receiver. To avoid the complexity and real estate of a polarization-diversity receiver, MIRAGE leveraged the low PDL of its SOI platform (employing 340 nm top silicon thickness) to design polarization-insensitive wavelength demultiplexers. The devices were based on a DI structure, equipped with heater tuning sections for compensating potential wavelength uncertainties induced by fabrication tolerances at the VCSEL or SOI processes. To account for the polarization dependent frequency shift (PDFS) of the SOI platform that varies considerably with the fabrication tolerances, overall birefringence was engineered and an additional tuning section was included in the DEMUX design to further control it.
A schematic of the polarization-insensitive wavelength demultiplexer (DEMUX) in shown in Figure 6. The design is based on the utilization of two waveguide segments inside the MZI branch that differ in terms of width. A 3D impression of the design is depicted in Figure 6.
As shown in the figure, both arms comprise two different segments each one equipped with an individual heating electrode. The width difference between the two segments is properly chosen so as to realize a “pseudo” dispersion compensation scheme inside the arms of the DEMUX design. Estimation of the group indices for TE and TM modes reveals that their relation is strongly dependent on the waveguide width. As a result, with careful design of the waveguide width, it is possible to achieve equal overall group index between TE and TM polarization.
The transfer function of the MIRAGE polarization-insensitive wavelength demultiplexer is shown in Figure 7(a) below. The figure reveals that 7 nm FSR is achieved for both TE and TM polarization verifying the feasibility of the proposed two-segment concept. Furthermore, Figure 7(b) demonstrates that individual tuning of the TE and the TM transfer functions is possible by operating the heating elements of either the first or the second branch segment. The solid lines correspond to a spectral mismatch lying in the range of 0.3 nm with the heaters being at the OFF state while, by turning on the heating electrodes this difference can be reduced to zero (dotted line).
Low-loss, polarization-insensitive in-plane couplers were targeted in MIRAGE for the efficient interfacing of the developed silicon nanophotonic components with elements featuring a larger MFD, such as optical fibers and glass waveguides. Throughout the project, four design phases were carried out.
Phase 1 concerned the design and optimization of the simple mode converter based on the well-known configuration that includes a tapered silicon waveguide (with adiabatically reduced width) cladded in a polymer waveguide with larger dimensions.
Phase 2 aimed to increase the overall fiber-to-chip coupling efficiency and followed a co-design methodology, taking into consideration all the optical components involved in this coupling scenario i.e. glass fan-out and SU8 Spot-Size Converter (SSC) and optimizing the overall design conforming to the technological limitations associated with both components. To achieve gradual and smooth power conversion, avoiding coupling to higher order modes, the linear taper profile was replaced by a design that follows an exponential increase of the taper width, revealing significant enhancement of the conversion efficiency particularly for the TM polarization (see Figure 8).
Phase 3 introduced a slightly modified approach employing an oxide overcladding on top of the strip silicon waveguides. The overcladding enables the straightforward deposition of a metallization layer on top of the photonic circuitry in order to realize thermo-optic or electro-optic control of the integrated devices. To retain the conversion efficiency of the SSC despite the increased distance between the silicon and polymer waveguides, a thin SiN film was placed between the SU8 polymer and the oxide cladding, so as to improve the overlap between the fundamental modes and enhance the coupling strength of the converter. An exhaustive study of the SSC design parameters resulted in a 5-segment taper profile with a 1D polymer taper, as shown in Figure 9. Overall glass-to-silicon coupling losses are less than 1 dB for both the TE and TM modes. The spectral behavior of the SSC was also simulated and conversion efficiencies well beyond 90% for both TE and TM polarization were estimated.
Phase 4 focused on developing an efficient SSC design without the SiN layer, given that the SiN film complicated the fabrication process flow in MIRAGE. A novel SSC design was generated to tackle the fabrication and process limitations in the project. The scheme involves a 2 degrees angled 3D glass waveguide assembled on a SiPh platform, whereas efficient mode conversion is realized via the simultaneous and reverse tapering of the two waveguide cores that increases the coupling performance and reduces the coupling length. Furthermore, the concept alleviates the edge chip scattering losses (a daunting issue of the flip-chip adiabatic couplers) thanks to the angled approach. Figure 10 depicts the proposed coupling scheme. The 3D glass waveguide exhibits a mode diameter of about 7um and it relies on the 3D waveguide inscription technology developed by Optoscribe.
The resulting taper shape is shown in Figure 11 (a) revealing a rather slow slope from 170 nm to 240 nm and fast transitions before and after that. The minimum silicon width was 150 nm so as to enable standard photolithography and avoid e-beam.
The overall TE glass-to-silicon coupling efficiency was found to be 98% while the coupling length was as low as 120um. A sideview impression of the TE propagating field is shown in Figure 11(b). The effect of the lateral assembly misalignments on the coupling efficiency was also briefly investigated using the EME solver. The results shown in Figure 11 (c) and (d) indicate adequate tolerance to lateral misalignments both along the y- and the x-axis, enabling the use of low-cost passive alignment assembly equipment.
The MIRAGE optical engine includes glass-based interposer interfaces that are used in order to facilitate optical interfacing of the transmitter and receiver prototypes with multi-core fiber (MCF). These glass interfaces make use of 3D embedded waveguide circuits produced using ultrafast direct laser writing technology that has been developed by Optoscribe and allows efficient rerouting of the core geometries of the multi-core fiber to the linear array for direct butt coupling to the SOI platform.
Within MIRAGE, the following glass interposers have been developed:
- 4-core MCF interposer, for interfacing the MIRAGE QSFP AOC with a 4-core MCF.
- 7-core MCF interposer, for interfacing the MIRAGE CXP AOC with a twin 7-core MCF array. Six cores are used in each 7-core MCF so as to provide 12 lanes of communication.
- 2×6 to 3×4 glass interposer, for interfacing the MIRAGE CXP AOC with three MIRAGE QSFP AOCs (breakout cable).
A schematic of the MIRAGE CXP, QSFP and breakout interface is shown below.
4-core MCF interposer
After detailed evaluation of commercially available 4-core fibers, the Fibercore SM-4C1500 was selected to be used in MIRAGE due to its consistency in terms of core spacing across the fiber. A 4-core glass interposer design was produced in order to match this fiber geometry. The waveguides were designed to mode-match to the multicore fibre, with an MFD of 10 μm, with a diameter of 8 μm. The laser inscription technique for waveguide fabrication used by Optoscribe produces waveguides with a square or rectangular cross section, in contrast to circular or asymmetric shapes commonly produced when using ultrafast laser writing. This property allows the waveguides to be treated and compared directly to conventional lithographically produced planar waveguide circuits.
The waveguide paths were designed and laid out in 3D using Optoscribe’s automated layout tools, allowing arbitrary placement of input and output coordinates of each waveguide. Figure 13 below shows a cross sectional microscope image taken in transmission mode of the 4 core interposer fabricated with 78 μm core-core spacing (left), as well as a stitched set of top down transmission microscope images showing the transition from a linear array at 127 μm pitch to a square arrangement with 36.25 μm pitch over a 10 mm length (right).
The insertion loss results for the MIRAGE 4-core MCF interposer were measured to <0.65 dB for all cores of the MCF.
7-core MCF interposer
The 7-core MCF interposer was designed according to the geometry of the Fibercore SM-7C1500 which was found to be superior both in quality and usability compared to other commercial high-port-count MCFs that were characterised. Figure 14 shows a schematic diagram of the layout alongside an image of a fabricated 7-channel fanout in a glass substrate.
At the next step, a dual 6-channel glass interposer design was produced in order to match to the geometry of the two Fibercore MCFs enclosed in the dual channel FVA. The central core of each 7-core MCF was not coupled to a waveguide, thus resulting in a 2×6 geometry matched to the 6 outer cores of the 7-core MCF. This 2D array of waveguides transitioned to a 1D linear array for coupling to the SOI waveguides. Figure 15 below shows a schematic representation of the device design. The fabricated waveguides have a mode field diameter of approximately 7 μm compared to the MCF mode field diameter of 8 μm.
A maximum insertion loss of 1.1 dB was observed for one channel with all other channels demonstrating losses of ≤ 1.0 dB.
2×6 to 3×4 glass interposer (breakout)
Interfacing the glass interposer with the MCFs requires the fibers to be housed in an FVA. This allows the MCFs to be held in a fixed geometry and securely bonded to the end facet of the interposer. Since there are multiple MCFs interfacing at the input and output of the interposer the fibers must be rotationally aligned within the FVA. This is a key design requirement of the multi-channel MCF FVAs as any rotational variation between the fibres will result in misalignment from the waveguides in the glass interposer. Ultrafast laser inscription can easily produce custom geometries to compensate for any rotational misalignment of the MCFs, however it is desirable to standardise the design of the interposer in order to prevent the need for a new design with every device.
Dual-channel FVAs with 7-core fibers as well as three-channel FVAs with 4-core fibers were characterized and a 12-channel interposer design was developed to match their geometry. The waveguide layout of the fiber-to-fiber break-out device was designed in 3D using Optoscribe’s automated layout tools, allowing arbitrary placement of input and output coordinates of each waveguide.
The interposer was measured to provide low loss coupling (≤ 2.3 dB per channel) from 3 × 4-core MCF to 2 × 7-core MCF (using only 12 channels) capable of interfacing between the MIRAGE CXP and QSFP modules. The cross-talk of the breakout interface was also measured for all channels and was found to be below -47.2 dB.
WP4: Development of optical and electrical active components
WP4 focused on the development of the active electronic and optoelectronic components used in the MIRAGE optical engine. These comprise single-mode, long-wavelength VCSELs as well as BiCMOS VCSEL drivers and TIAs.
Single-mode, long-wavelength VCSELs
Vertical-cavity surface-emitting lasers (VCSELs) are the transmitter of choice for short-reach applications due to their low cost, energy efficiency, and compact footprint. InP-based VCSEL emitting at long wavelengths (i.e. 1.3 and 1.55 μm) have gained large interest due to their intrinsic low power consumption (low band gap) and low losses in silicon waveguides and silica-based optical fibers which allows transmission distances of several kilometres, finding application in both datacom and telecom networks.
In the framework of MIRAGE, we have demonstrated an ultra-short cavity VCSEL (USCV) emitting at 1.55-μm and allowing:
- maximum small-signal modulation bandwidth of 22 GHz at room temperature operation (uncooled). For comparison, wafer-fused 1.3-μm VCSELs shows a maximum bandwidth of ~10 GHz, while 1.55-μm VCSELs using high-contrast gratings reached ~8 GHz (2013). The bandwidth of the USCV presented in this work is 2 times higher than any other long-wavelength directly-modulated VCSEL. Thanks to this large bandwidth, TUM has generated a record-high 50 Gb/s non-return-to-zero (NRZ) signal without any equalization which is detected error free as shown in Figure 16 (b).
- energy efficiency. The USCV achieved a bandwidth of 9 GHz for 1.4 mW DC power consumption, while the wafer-fused 1.3-μm VCSELs shows similar results for a DC power consumption larger than 28 mW. We have demonstrated a factor of 20 savings in energy consumption.
- single-mode operation. To our knowledge, the USCV is the only published single-mode VCSEL with bandwidth of 22 GHz.
- design of a VCSEL with a calculated small-signal bandwidth of 26 GHz. Combining the USCV design with a novel double-mesa structure and a highly strained active region as shown in Figure 16 (a), TUM has simulated an 20% bandwidth enhancement. These lasers will be fabricated in the near future.
Making the InP-based long-wavelength VCSEL technology competitive with the short-wavelength GaAs-based one is a big step towards the evolution of low-cost energy-efficient transceivers capable of interconnecting large datacom and telecom networks with the same SMF infrastructure and allowing, in the near future, terabit connectivity.
BiCMOS VCSEL drivers and TIAs
In the framework of MIRAGE, IMEC-INTEC has developed two key BiCMOS electronic components:
- VCSEL drivers with on-chip retiming, NRZ to PAM-4 conversion, electronic equalization circuits and programmable bias/modulation current sources for the transmission of optical multi-level signals with common-anode VCSEL arrays.
- Photodiode TIA arrays with linear post-amplifier, AGC and offset compensation to support the reception of optical multi-level signals.
The VCSEL driver channel architecture is shown in Figure 17(a). The driver features a 4-tap symbol-spaced feed-forward equalizer (FFE) with a selective falling-edge pre-emphasis (SFEP). Two single-ended binary data streams MSB and LSB are synchronized with each other through retiming flip-flops before they are combined at the output stage. Dimensioning the tap coefficients A0 to A3 in the MSB path twice as large as in the LSB path creates the multi-level current. This current can be pre-distorted by changing the magnitude and the sign of the coefficients A1 to A3. Each tap can be enabled and configured on demand. This allows determining the optimal topology based on power efficiency and transmission performance. Typically the falling edge of the VCSEL signal is slower than the rising edge, which results in pulse width distortion (PWD). This non-linear effect can close the bottom eye in a PAM-4 eye diagram, effectively limiting the total performance. This effect is compensated by the insertion of the selective falling-edge pre-emphasis (SFEP) block in the channel. This block generates a pre-emphasized current pulse only when both MSB and LSB experience a transition from high to low, hence the name selective. The VCSEL driver chip was fabricated in 130 nm SiGe BiCMOS technology from ST Microelectronics and measures 1 mm x 2.8 mm. The chip layout is shown in Figure 17(a).
The TIA channel architecture is shown in Figure 17(b). The TIA chip features a low-noise linear data path with an event-driven gain/bandwidth control loop. The data path contains all high-frequency stages. The first stage, the TIA core, converts the current going into pdan to a voltage, which is then fed to one of the inputs of the differential main amplifier and 50 Ω output buffer. Multi-level modulation requires a linear receiver front-end to preserve the different eye openings as a traditional, limiting, NRZ receiver would compress the outer eye diagrams. In order to achieve the required linearity and bandwidth for PAM-4 detection, an event-driven gain/bandwidth control loop is developed to avoid saturation in the various amplifier stages, while providing sufficient gain to ease further signal processing in a system test bed or demodulator. The TIA chip was fabricated in 130 nm SiGe BiCMOS technology from ST Microelectronics and measures 1 mm x 3.7 mm. The chip layout is shown in Figure 17(b).
The performance of the MIRAGE driver is first measured through electrical probing. Clear PAM-4 electrical eye has been observed up to 36 GBaud (72 Gb/s). The optoelectronic performance is tested by wire bonding the driver to a 22 GHz VCSEL from TUM. Pre-distorting the output current of the VCSEL driver with a 4-tap FFE significantly reduces the inter-symbol interference of the PAM-4 signal as can be noticed in the 28 GBaud eye diagrams of Figure 18(a). This conclusion can also be derived from the BER plots at 25 and 28 GBaud in Figure 18(b,c). Considering an RS(544,514) code with a pre-FEC BER limit of 5.2 x 10-4, sensitivity is improved by 1.4 dB at 25 Gbaud and 3.8 dB at 28 Gbaud. Performance at 0 dBm is well below FEC limit with a BER smaller than 10-6 and error free at 25 Gbaud. With a record length of 2.8 x 107 bits, this corresponds to an upper BER limit of 1.7 x 10-7 at a 95 % confidence level. Opting for a 3-tap FFE at 56 Gb/s results in 9.6 pJ/bit, which is twice as efficient as recent 56 Gb/s NRZ drivers, while the 4th tap could become crucial when compensating chromatic dispersion in longer SMF links and should be further investigated.
The MIRAGE linear optical receiver was tested in a separate setup. The transmitter is comprised of a continuous-wave 1550 nm laser and a 25 GHz Mach-Zehnder Modulator (MZM), modulated by an electrical PAM-4 signal from an AWG yielding a 5.9 dB ratio between the optical powers corresponding to the normalized levels +1 and −1. The results of the BER measurements are shown in Figure 19(b), along with our preliminary results (red line) and the forward error correction (FEC) BER limit of 10−3. The BER curves are the combined result of both high and low gain modes, at each point utilizing the mode yielding the lowest BER. As can be seen in the figure, the BER limit at 56 Gb/s (64 Gb/s) is achieved for average optical input powers between −8.4 dBm (−7.0 dBm) and at least 1.6 dBm (1.7 dBm) when selecting the appropriate TIA mode. Eye diagrams were measured at 56 Gb/s and 64 Gb/s and shown in Figure 19(left).
WP5: Optical/electrical 3D chip integration and AOC assembly
WP5 addressed the development of 2.5D and 3D integration processes and associated technologies. Work focused on the following activities:
- Silicon interposers with through silicon vias (TSVs)
- Combined photonic-electronic silicon interposers for 3D integration
- Bonding of electronics and optoelectronics for 3D integrated chips
- Bonding of electronics and optoelectronics for 2.5D integrated chips
- Design and fabrication of prototype demonstrators
Achievements in the above activities are outlined in the following sections.
Silicon interposers with through silicon vias (TSVs)
With the increasing use of 3D packaging techniques, interposers with TSVs are receiving more and more interest. TSVs provide electrical contacts on the backside of chips, facilitating assembly on PCBs with industry-compatible flip-chip techniques. Thus 3D interposers are an elegant way of reducing assembly costs and shortening electrical interconnections, which can compromise signal integrity and increase power consumption.
MIRAGE has capitalized on the technology of the elegant tungsten TSV-last process developed by AMS. Within the project the bandwidth of the TSVs was increased substantially from less than 10 GHz to above 40 GHz. During the project several design variations of silicon interposers with tungsten TSVs were designed and fabricated. TSV height (100μm and 200μm) and of the TSV diameter (40μm and 80μm) were varied and the 3dB bandwidth was measured using bespoke S-parameter structures, for the following combinations:
- 80 μm diameter, 200 μm height, std isolation oxide thickness: 23 GHz bandwidth
- 40 μm diameter, 200 μm height, std isolation oxide thickness: 28 GHz bandwidth
- 40 μm diameter, 100 μm height, std isolation oxide thickness: >40 GHz bandwidth
There is a clear trend visible that with smaller diameter and less TSV height a bandwidth of more than 40GHz can be achieved. This excellent result is more than sufficient for the needs of the MIRAGE demonstrators.
To facilitate characterization of the TSVs, s-parameter structures were developed. Typical s-parameter structures consist of 2 TSVs for transmitting the signal to the wafer backside and another TSV for the back-transmission, i.e. in order to find out the signal loss in one TSV it is required to measure the signal attenuation in two TSVs in series, which increases the noise. A new type of s-parameter structures was designed, following the idea that the same signal attenuation will take place in a TSV that is not directly in the signal path, but that is electrically closely attached to the signal path.
Combined photonic-electronic silicon interposers for 3D integration
MIRAGE developed the methodology to generate silicon interposers with photonic and electronic functionalities. This is achieved in MIRAGE by wafer bonding of the silicon electronic interposer wafers, developed by AMS, with silicon photonic wafers fabricated by AMO. The combined process flow for the fabrication of the silicon photonic/electronic interposer boards at the two foundries has been developed. The assembly flow for attaching electronic and optoelectronic components on the silicon boards has been developed, thus enabling the design of a QSFP transceiver prototype. Requirements coming from the assembly point of view, concerning e.g. compatibility of the required processes for implementing the SU8 in-plane couplers for low-loss fiber coupling, are all integrated in the process flow.
A combined fabrication run was carried out, proving the validity of the developed process flow and the smooth cooperation of the partners. The wafers were started at AMS with the processing of a basic alignment mark, and then sent to AMO, where the waveguides were processed. As the minimum wave guide structures went down to 50 nm, the electron beam lithography system of AMO had to be used. Further processing of the interposer with the metallisation above the wave guides and the TSV processing with metallisation on the back-side of the TSV was performed by AMS. The opening of the window for the adiabatic coupling of light was again a cooperation: AMS did the oxide etch and the stop-layer removal, while AMS released the wave guide and developed the processing of the SU-8 polymer wave guide. It should be noted that the optical properties of the silicon photonic structures were only slightly affected by the overall process flow, introducing a penalty of the order of 0.9 dB/cm and 0.9 dB/GC.
Bonding of electronics and optoelectronics for 2.5D integrated chips
A method for the flip-chip assembly of VCSELs on conventional grating couplers was developed, tacking with the 10 degrees off-vertical coupling of the latter. This concept was necessary in order to allow reliable low-cost assembly of the VCSELs on standard silicon chips (e.g. available in PDKs of commercial MPW services) that were used in the 2.5D configuration of the MIRAGE optical engine.
The developed approach relies on SU8 prisms that are defined on top of the GCs using non-uniform laser ablation process. The prism enables perfectly vertical coupling from the bonded VCSEL to the GC. The VCSELs are flip-chip bonded on top of the silicon GCs employing the laser transfer printing assisted thermocompression technique. A schematic of the approach is shown in Figure 24.
The simplicity of this technique lies in the fact that the prism angle can be tuned just by adjusting the laser energy and sample scan speed. Micro-bumps of indium solder with ~20 μm diameter and ~7 μm thickness were then printed on the VCSEL bonding pads employing the laser transfer technique. The final step in the assembly was to flip-chip bond the VCSEL chips onto the GCs with SU8 prism fabricated on top. The VCSEL chips were diced using the Timebandwidth Duetto laser at a fluence of 3.3 J/cm2.
Measurements yield a <1 dB excess loss due to the overall assembly process. The main contributing factor for the excess loss is attributed to the misalignment during bonding as the flip-chip process involved passive alignment of the VCSEL and SOI chip. Figure 26 shows the optical spectrum measured at the output of the waveguide using an optical spectrum analyzer with a resolution of 0.05 nm and a dynamic range of 40 dB, at a driving current of 5 mA. The spectra were continuously recorded over a period of 45 minutes for different current values and no significant effect of backreflection from the prism (no shoulders around the main peak) was observed.
Bonding of electronics and optoelectronics for 3D integrated chips
A 90 degree out-of-plane coupling mirror was developed at the tip of the SU8 spot size convertor, which will be used to couple light from the SOI towards the photodiode array, and towards the multicore fiber array. This process was developed at IMEC-CMST, based on Excimer laser ablation. The process was optimized in terms of coupling angle (45 degrees), as well as the deformation and contamination inherent to laser ablation was eliminated, by covering the SU8 waveguide with a temporarily protective coating (resist), which can be washed away after completing the process. Microscope images of the cross-section are included below.
The bonding technology for all electronics and optoelectronics was developed in view of maximizing compatibility of the different processing steps. The developed process was based on Au stud bumps and the associated process was investigated in detail by IMEC- CMST, in order to limit the distance from active device to the SOI, and in addition comply with the limitations in bonding temperature imposed by the MIRAGE VCSELs. For that reason, the Au stud bumps are flattened, and the bonding is achieved using laser transfer printed Indium solder, which allows for assembly at low temperature (Figure 28). Instead of using gold to gold stud bumping at high temperatures, a low temperature bonding process based on Indium solder was applied.
Instead of using gold to gold stud bumping at high temperatures, a low temperature bonding process based on Indium solder was applied. The laser transfer printing process for Indium solder deposition on a chip level was already established within the first two years of the project. However, the formation of InAu intermetallics was studied in more detail in the last reporting period, as a function of the applied temperature and pressure. InAu intermetallics are stable up to very high temperatures, which allows for a stable assembly up to very high temperatures. A few results of the SEM_EDX analysis are included above, indicating the presence of AuIn2 compounds in the interface (thermally stable up to > 500 degrees C). All assembly steps associated to the 3D integrated configuration of the MIRAGE optical engine have been developed on test samples.
Design and fabrication of prototype demonstrators
The developed process flow and combined design rules were applied to design a number of prototype demonstrators. Different configurations of the MIRAGE optical engine were considered, such as assembly of active optoelectronics on a PCB, assembly on an electrical interposer and assembly on an electro-optical interposer. Examples are shown in the following figure.
WP6: Performance evaluation and system testing
WP6 concerns the evaluation of the MIRAGE components and prototypes. State-of-the-art testbeds were setup by the project partners and were customized to accommodate the requirements of MIRAGE.
Main results are outlined below:
PAM-4 modulation up to 80 Gb/s with MIRAGE VCSELs
The performance of the MIRAGE VCSELs was evaluated at baudrates beyond 28 Gbaud with PAM-4 modulation. The VCSELs had a 3-dB bandwidth of 20.5 GHz and were probed for the experiment. Figure 30 illustrates the experimental setup, based on an 8-bit, 65 GSa/s Arbitrary Waveform Generator (AWG) generating directly the PAM-4 signal driving the VCSEL. Raised Cosine (RC) pulse-shaping with a roll-off factor a=1 was implemented in order to confine the bandwidth of the signal to the main lobe.
Figure 31 depicts eye diagrams at 32 Gbaud and 40 Gbaud, acquired with a 70 GHz equivalent time oscilloscope before (back-to-back) and after propagation over 500 m.
BER measurements were performed to the received signal after digitization with a 33 GHz, 80 GSa/s real-time oscilloscope and offline resampling and symbol timing recovery, followed by static equalization to compensate the channel bandwidth limitations. Automatic thresholding for symbol detection followed by BER assessment were performed so as to evaluate the received PAM-4 signals both in back-to-back configuration and after transmission over 500 m SMF. The BER performance was realized by comparing the received sampled signal to the original bit sequence and counting the actual erroneous bits of the received signal. Figure 32 presents the measured bathtub curves. At 32 Gbaud and average input power ranging between -10 dBm and 0 dBm the obtained BER curve lies below Hard FEC limit in both transmission scenarios. Moreover, at 40 Gbaud a reasonable degradation of the measured BER was noted, mainly due to the fact that the 20 GHz 3-dB bandwidth of the VCSEL posed a corresponding limit to the lowest measurable BER. Nevertheless, the achieved BER at 40 Gbaud was still below Hard FEC limit even after propagation over 500 m. It should be noted that the limiting operation of the available receiver that was used in the setup caused an additional penalty to the signal especially for high received power levels.
MIRAGE single-mode VCSEL link
A PAM-4 experiment was held in order to evaluate the performance of a full link implemented with the MIRAGE Tx and Rx platform. The experimental setup is depicted in Figure 33 and relied on an Arbitrary Waveform Generator generating two NRZ streams that were supplied to the MIRAGE transmitter, which formed the PAM-4 test signal after retiming. An Erbium Doped Fiber Amplifier and a Variable Optical Attenuator (VOA) were used in order to adjust the incident optical power in the MIRAGE linear receiver, enabling the measurement of Bit-Error-Rate vs. incident power.
The PAM-4 optical eye diagrams at 25, 28 and 32 Gbaud for the back-to-back, 500 m and 2 km transmission scenarios are presented in Figure 34. The effect of bandwidth limitations is evident with the increase of the baud rate. Moreover, propagation through the 2 km of SMF impairs the signal due to fiber dispersion at 1550 nm.
BER measurements were obtained after acquisition of both differential outputs of the received PAM-4 signal with a 33 GHz, 80 GSa/s Agilent Infinium real-time oscilloscope. Subsequent offline processing was comprised of re-sampling, symbol timing recovery followed by a static equalizer to (partially) compensate the channel bandwidth limitations and automatic thresholding for symbol detection. The BER performance was evaluated by comparing the received sampled signal to the original bit sequence and counting the actual erroneous bits of the received signal. Figure 35 presents the measured BER curves at 25, 28 and 32 Gbaud for the aforementioned transmission scenarios, plotted against the average received optical power derived from the measured photocurrent. The achieved BER for the single mode VCSEL link lies well below the FEC limit both at 25 Gbaud and 28 Gbaud, whereas only after propagation in 500 m at 32 Gbaud fails to reach the FEC limit mainly due to the effect of dispersion. The power penalties after transmission in 500 m and 2 km SMF at 25 Gbaud are 0.2 dB and 0.6 dB respectively for a BER equal to 6·10-4. Similarly, the received 28 Gbaud signal exhibits a power penalty of 1.8 dB for a BER in the order of 5·10-4.
The MIRAGE receiver was also tested with an externally-modulated reference transmitter to investigate its capabilities. The experimental setup is shown in Figure 36.
Typical eye diagrams at 25, 28, 32 and 35 Gbaud are depicted in Figure 37.
The BER performance of the implemented link was evaluated using the same procedure as explained above. No equalization was applied in the waveforms acquired by the real time oscilloscope. Figure 38 presents the measured bathtub curves for 25, 28, 32 and 35 Gbaud input signals plotted against the average received optical power, derived from the measured photocurrent. As observed, at 25 Gbaud and average input power ranging between -6 dBm and +3 dBm, the received signal exhibits zero errors, which corresponds to an upper 95 % confidence limit of 2.9×10-7. It is clear that even at 35 Gbaud the minimum achieved BER lies below the FEC limit, proving the suitability of the MIRAGE linear receiver for long-reach optical interconnects.
WP7: Applicability, techno-economical assessment and integration standardization
WP7 aimed to raise awareness of the project and to maximize the exploitation potential from the developed technologies to the project partners. The following types of activities were carried out within MIRAGE:
Exploitation of project foreground knowledge
- All partners elaborated on their exploitation plan and identified opportunities for application of the developed technology in their roadmaps. The high level of integration in MIRAGE and the particularities of the developed technology open new opportunities for collaboration between the industrial partners as well as for use cases in other fields outside the optical interconnects business.
- Collaborations with other initiatives were setup. MIRAGE interacted with the following organizations and projects: EPIC, PARADIGM, ECOIC, PhoxTrot, ePIXfab, DISCUS.
- The MIRAGE consortium followed an industry-driven IPR policy that motivated IP protection prior to publication. As a result, five patents and one provisional patent were filed throughout the duration of MIRAGE.
Dissemination of project foreground knowledge
- MIRAGE partners were particularly active in disseminating project outcomes. The state-of-the-art results obtained within the project resulted in a large number of scientific publications (66) in top-ranked journals and conferences.
- MIRAGE partners also participated in workshops, events and expositions and presented the project concept and outcomes. Overall, MIRAGE partners disseminated the project activities in more than 12 events.
- The MIRAGE website was prepared and regularly updated by the project coordinator. In its public part, the website provided information on the project objectives, updates on its achievements and contact details to its partners. Information was presented in an incremental manner so as to address individuals with different levels of knowledge in the field.
- Dissemination to the general public was facilitated with the MIRAGE video clip, which presents the project’s approach and potential impact in a simplified manner accessible to individuals without deep knowledge in the field.
Optical interconnects play a central role in ICT systems, extending beyond the limits of the Datacom sector and penetrating consumer electronics. According to Infonetics the overall data center networking market alone will reach $21.85 billion by 2018 on an 11.8% growth rate. This burgeoning market is driving growth in optical interconnects, as they represent an integral part of its ecosystem (along with switches and network interface cards). Lightcounting predicts that by 2018, the market for Ethernet optical interconnects (1/10/40/100 GbE) will reach an aggregate of approximately $2.2 billion. Chip-level optical interconnects are also gaining traction and are expected to generate $990M in revenues by 2020, as foreseen by CIR.
The overall global data center market was estimated to be worth ~$150bn in 2014, growing at 9-10% a year. Already there is over 1.8 billion square feet of data center space in 8.6 million data centers worldwide. Although North America led the early deployment of data center, the industry has globalized rapidly as shown by the global distribution of data center space. Whilst North America is still significant, data center area in China has grown rapidly Europe represents 26% of the data center area. The market for the equipment contained in those centers is worth ~$114bn in 2014/15 and forecast to grow by over 14% annually, driven by both replacement of existing equipment and new data center build.
MIRAGE is well-positioned to claim a large share of this burgeoning market. The project has introduced a set of technologies (single-mode, WDM, SDM, PAM-4 modulation) capable of scaling interconnects capacity individually or as a combination, according to the requirements of the application. These technologies are arguably the key enablers for future optical-interconnects suited to the capacity and reach requirements of scale- out datacenters. The project also took considerable care to address system integration and packaging, recognizing their importance as key contributors to the overall cost of optical interconnects, and thus sought to provide a viable path for integration of its state-of-the-art components into value-added products. Three configurations have been actively investigated in the project, starting from current established production practices and extending to more forward-looking concepts that vouch for further cost savings and component miniaturization once they reach the market. It should be noted that although assembly and packaging is currently dominated by the far-East, application of 2.5 and 3D integration approaches in Datacom and Computercom (as pioneered in MIRAGE) offers a unique opportunity for Europe to recapture assembly and packaging on its soil.
The MIRAGE consortium is industry-driven and includes players across the value chain, enabling commercialization of the technology with a Europe-based supply chain. Most importantly, the consortium includes a leading vendor of optical interconnects, Mellanox, providing a viable path to the market. Mellanox has proven consistent leadership in each new technology generation as it was the first to market end-to-end solutions for 25, 50 and 100 Gb/s. According to Crehan Research Group Mellanox is the fastest growing Ethernet Vendor, whereas the company is the leading vendor for Infiniband, which is dominating the HPC application space. With revenues of $196.8 million and over 2000 employees in Europe, Mellanox is a competent player with a considerable socio-economic impact in Europe. The company sees substantial value in the technologies developed within MIRAGE as key enablers for sustaining growth in optical interconnects and reinforcing Europe’s share in the global scene.
Wider societal implications
Today’s data-affluent society relies on datacenters to store and rapidly access massive amounts of information. The internet, as the means of accessing this information, has evolved into a key driver for economy, as well as into a means for social interaction and social inclusion. Reflecting its content-centric design, the entire internet is built around datacenters. Scaling internet performance and associated cloud services necessitates scaling of datacenter connectivity; more specifically intra-datacenter connectivity, since more than 2/3 of datacenter traffic concerns east-west connections between hosts inside the datacenter. MIRAGE technology aims to provide a viable solution for gracefully scaling capacity in datacenters, and can therefore underpin the societal implications of enhanced datacenter connectivity. Prominent examples are outlined below:
Supporting the digital single market. Data centers are the enablers for all types of digital goods and services. From value-added services offered by the cloud to instant content delivery provided by edge computing, datacenter technologies offer unlimited opportunities affecting economic growth and access to knowledge. Optical interconnects are essential to remove current barriers in the access of online services and create an environment of equal opportunities, where digital networks and services can prosper.
Increase supercomputer achievements: Optical interconnects are essential in high-performance computing (HPC) systems. Scaling the performance of HPC is expected to have a significant impact in a broad variety of societal challenges, giving rise to breakthroughs in medicine, material design, climate modelling and more.
The Project’s Public web-site: (http://www.ict-mirage.eu/)
The public website of MIRAGE Project website played a key role to the dissemination and the exploitation of the project results. The website was designed to fulfill the following objectives:
- To present the profile of MIRAGE to the visitors of the site (members of the scientific community, people from industry, general public).
- To efficiently present the MIRAGE specific objectives, methodology and progress on the research activities. This targets in particular the members of the scientific community and the people from industry and aims at attracting their interest, increasing the visibility of the project and creating a momentum for MIRAGE technology and prototypes in the next years.
- To establish the website as an interesting point of reference from people coming from different scientific fields, i.e. polymer science, high‐speed electronics and optoelectronics and optical communications. To fulfil this, the website has been designed so as to contain information and news from recent developments in these fields and announcements for relevant events (conferences, workshops, etc).
- To become a point of reference for the consortium members concentrating the main documents and enabling flow of information between the partners.
- To facilitate efficient information flow and submission of documents to the EC.
The home page of MIRAGE’ public website.
The MIRAGE Consortium
RAMPLAS: Silicon-based, integrated Optical RAM enabling High-Speed Applications in Computing and Communication
[September 2011 – February 2015]
PCRL participated in the EU-funded project RAMPLAs, a cross-disciplinary project that aimed to revisit the fundamentals of optical RAM technology and to develop the first 100GHz RAM chips, fostering their effective application in ultra-fast energy-efficient computing architectures and optical communication systems. RAMPLAS followed a holistic approach and blended innovation in computer science, optical design, photonic integration and semiconductor physics. Novel epitaxial methods for the fabrication of ultrafast dilute-nitride-antimonide on GaAs (InGaAsNSb/GaAs) SOAs acting as active elements for the 100GHz optical RAM chips and being capable of uncooled operation. Heterointegration techniques on established SOI technology paved the way towards the development of densely integrated optical multi-bit RAMs and kByte capacities. The research outcomes of RAMPLAS have been evaluated in a solid proof-of-concept validation plan based both on simulations and experiments, intending to set the scene for new paradigms in Computing, Communications and Test & Measurement. PCRL’s role was to identify application scenarios of the optical RAM in the latter two fields and to evaluate the system-level performance of the RAM-chips.
Direct 100G connectivity with optoelectronic POLYmer-InP integration for data center Systems
[October 2010 – January 2014]
POLYSYS aimed to realize for the first time serial 100 Gb/s direct connectivity in rack-to-rack and chip-to-chip data communications systems. In specific, POLYSYS focused on the development of photonic and electronic components operating directly at 100 Gb/s based on electro-optic polymers enabling the best possible material compatibility with current polymer-based optical backplanes. The technical objectives of POLYSYS were achieved through the cost-effective polymer material system for realizing the electro-optic components and the utilization of InP for developing high-performance optical and optoelectronic components.
After 40 months of development efforts it can be said that POLYSYS has been extremely successful in helping EO polymers evolve from a device specific technology into a broader purpose platform for small-scale and high-performance integrated circuits for datacom applications. Achievements to this direction include:
- The monolithic integration of MMI couplers and tunable Bragg-gratings together with MZMs on EO polymer chips.
- The hybrid integration of InP chips (laser diodes, gain chips, photodiodes) with EO polymer chips and the development of lasers with 17 nm tunability combining InP gain chips with monolithic Bragg-gratings.
- The integration of EO polymer chips with InP-DHBT circuits using wire-bonds and the packaging of integrated transmitter modules.
At the same time, POLYSYS has also been extremely successful in extending the limits of InP photodetector technology and developing quad arrays of pin-photodiodes and pinTWAs with potential for 100G operation, as well as in advancing the state-of-the-art of InP-DHBT technology and developing novel MUX-DRV circuits and twin-DEMUX circuits for operation at 100 Gb/s. Through the integration of all these components, POLYSYS has impressively achieved the final packaging of six out of the seven modules that had targeted:
- The 100 Gb/s transmitter
- The 2×100 Gb/s transmitter
- The tunable 100 Gb/s transmitter
- The 100 Gb/s integrated optical interconnect
- The 4×100 Gb/s pin-DEMUX receiver
- The 4×100 Gb/s pinTWA-DEMUX receiver
Four of these modules (100G Tx, 2x100G Tx, tunable 100G Tx and 4x100G pin-DEMUX receiver) were successfully tested and confirmed the potential for error-free operation at 80 and 100 Gb/s and transmission over SMF links of at least 1km without dispersion compensation, whereas the testing of a fifth one (4x100G pinTWA-DEMUX) will be completed after the final review meeting.
POLYSYS gained remarkable visibility through a variety of dissemination actions and prestigious publications (including the ECOC 2012 PDP), and succeeded in defining concrete exploitation plans by all partners. Significant achievements that are related to the actual exploitation of the foreground knowledge are the industrial strategic partnership between GigOptix and HHI in the last period of the project and the funding of a follow-up research project (http://www.ict-panther.eu/) that was based on the knowhow of POLYSYS.
RAMPLAS: Silicon-based, integrated Optical RAM enabling High-Speed Applications in Computing and Communication
[September 2011 – February 2015]
GALACTICO aimed to develop the photonic integration technology to disrupt the current transition from 10/40Gb/s to 100GbE optical long haul networks and at the same time to address the next capacity increase towards 400 Gb/s and beyond. To achieve this goal, GALACTICO has demonstrated photonic integrated circuits and modules combining technical and economic feasibility as well as a broad market potential. GALACTICO has invested in two technologies that leverage cost-effective PIC fabrication in foundries; a) Silicon Photonics (SiPh) to implement the receiver interfaces and b) GaAs to implement the transmitter modulation interfaces.
On the “receive-side”, GALACTICO fabricated and demonstrated silicon nano-waveguide PICs that squeezed all the optical (signal coupling, polarization splitting, mixing) and opto-electronic (optical to electrical conversion) receive functionalities in record tiny, few-mm-scale chips. Fabrication was done using the standard toolset of a silicon foundry and through BiCMOS processes, opening the way for truly cost-effective “photonic BiCMOS”. On the “transmit-side”, GALACTICO fabricated GaAs modulator chips that integrate tightly all optical and opto-electronic functionalities (signal splitting, electro-optic modulation, polarization rotation/multiplexing) in modules that are well smaller than the current 100G standards set by the photonics industry. Fabrication was done leveraging cost effective fabrication in GaAs foundries that serve the mobile industry and run thousands of wafers per year.
GALACTICO delivered the receiver and modulator PICs as fully packaged modules and tested them in a series of lab experiments and field trials demonstrating the feasibility of delivering >200 Gb/s line rates using polarization multiplexed and multi-level coded signals (DP-QPSK, DP-16-64 QAM) being well aligned with upcoming optical transport system upgrades that foresee migration from 100G DP-QPSK to >200G DP-16QAM modulation formats. Being fully in line with development in Ethernet Alliance and IEEE 400G Ethernet Group, GALACTICO devices were qualified for integration in system portfolios that will deploy 400G interfaces with fully integrated optics hitting the right cost, size and technical feasibility points; i.e. all the requirements for quick and volume deployment of 100G systems as well as the sustained entry of 400G technology. By so doing, GALACTICO enabled key European industrial players to formulate and capture the growing OTN market, ultimately leading to new opportunities for high technology jobs within Europe.
Merging Plasmonic and Silicon Photonics Technology towards Tb/s routing in optical interconnects
[January 2010 – December 2012]
PLATON aimed to address the size and power consumption bottleneck in Data Centers and High-Performance Computing Systems (HPCS) by realizing chip-scale high-throughput routing fabrics with reduced energy consumption and footprint requirements. It intended to demonstrate Tb/s optical router prototypes for optical interconnects adopting plasmonics as its disruptive technology to reduce size and energy values. To achieve this, PLATON intended to deploy innovative plasmonic structures for switching applications and to develop novel fabrication processes for merging plasmonics with silicon nanophotonics and electronics. The enhanced functionality of PLATON’s platform was utilized to develop and demonstrate Tb/s routing, enabling the penetration of a merged plasmonics/photonics configuration in short-range blade and backplane data interconnects. PLATON’s optical board technology was expected to blend the functional potential of small-footprint, high-bandwidth plasmonic structures and the integration potential of plasmonics with the more mature SOI technology providing a new generation of miniaturized photonic components. Its main objectives span along the fabrication and demonstration of:
- a whole new series of 2×2 plasmonic switches with ultra-small footprint, very low power consumption and less than 1μsec switching times,
- a low latency, small-footprint 4×4 plasmonic thermooptic switch,
- an optically addressable plasmonic 1×2 switch capable of operating at bitrates in excess of 10Gb/s, and
- A 2×2 and a 4×4 Tb/s optical routing platforms relying on SOI motherboard hosting the plasmonic switching matrix and the IC header processor for application in optical blade and backplane interconnects.
System-level integration involved the demonstration of the packaged Tb/s routing prototype offering minimum space requirements and up to 1.12Tb/s throughput. Its performance was evaluated in a real WDM 40 Gb/s testbed for optical interconnects.
Pan-European Photonics Task Force: Integrating Europe’s Expertise on Photonic Subsystems
[May 2008 – April 2012]
EURO-FOS has been a network of excellence (NoE) focusing on photonic components and subsystems for optical communications, funded by European Commission (EC) under the 7th Framework Programme (FP7). It started in May 2008 and concluded in April 2012. Its concept was conceived upon the observation that the map of European research in photonic communications technology includes a large number of active but smaller in scale academic laboratories distributed all over Europe. EURO-FOS has been an ambitious initiative to integrate expertise, equipment and resources from the 17 participating institutes towards the creation of a powerful Pan-European laboratory (eurofoslab) that scales more than linearly the potential of the individual institutes.
Using the structure of eurofoslab, the objective of EURO-FOS has been three-fold:
1) to enable partners make top-quality research through the sharing of ideas and resources and through the organization of large-scale experimental activities,
2) to enhance the collaboration of partners with industry through the agreement on common research thrusts and through the organization of a service provision platform addressing the needs of the photonics industry, and
3) to exploit the size of the network and organize a large number of education and dissemination activities spreading the word for photonics across Europe.
The operation of EURO-FOS supported the integration of all partners through frequent meetings, continuous interaction, participation in the set up of eurofoslab and participation in joint experimental activities (JEAs). Looking back, the things that EURO-FOS has achieved over its 4-year lifetime look really impressive:
The network succeeded in the development of eurofoslab through the registration of expertise and resources in the web-based inventories of the lab. A total of 839 items have been registered including more than 50 large-scale optical communications testbeds. Moreover, the network succeeded in creating the structure and the web-tools that enable searching and booking of appropriate equipment, planning of experimental activities and reporting on the progress on these activities, thus turning the vision of the Pan-European Laboratory into a reality.
Furthermore, EURO-FOS succeeded in integrating all participating institutes in its research activities. Research was organized within 4 centres of excellence (CEs) covering different discrete scientific areas of optical communications. To implement this research, partners organized a total of 66 JEAs involving the participation of a large number of external industrial and academic partners. The scientific outcome of these activities has been impressive: more than 400 EURO-FOS papers were published, some of them presenting world-record results and scientific “firsts”. Moreover, a total of 12 patents were filed aiming at turning the research output into exploitable technology.
Regarding the education and dissemination activities, EURO-FOS organized 7 workshops, 5 booths at major photonic conferences, 2 summer schools and 2 winter schools, and a large number of smaller-scale events addressing the general public and the local communities. As a result of the collaboration of the partners on educational activities, the network produced an education kit and organized the framework for joint supervision from senior staff of 13 PhD students working on the scientific topics of EURO-FOS.
Finally, EURO-FOS succeeded in bringing academia closer to industry. The network created a cluster of 29 industrial affiliates that have been closely monitoring and participating in the network activities, and an industrial advisory board (IAB) consisting of representatives from 6 of these affiliates (ADVA, NSN, ALU Germany, Tellabs, VPI and Finisar). Through continuous interaction with the members of the IAB, EURO-FOS has been trying to align its research topics with industrial trends and explore the interest of industry for the set up of a service provision platform in the field of photonic communications based on the expertise and equipment of European academic institutes. Although the idea of securing the self-sustainability of eurofoslab through the establishment of industrial collaborations on a pay-for-service basis has been over-optimistic, significant steps were made; as for example the identification of the need for further elaboration on the legal framework for the operation of such a service provision platform, the identification of industrial interest for specific technical services, the pilot run of “charge-free” service provision projects in the last year of the network, and the definition of a viable techno-economic plan for retaining the eurofoslab structure in the post EURO-FOS era with a 2-year horizon.
Terabit-on-chip: micro and nano-scale silicon photonic integrated components and sub-systems enabling Tb/s capacity, scalable and fully integrated photonic routers
[May 2008 – April 2011]
BOOM has been a photonic integration concept aiming to develop compact, cost-effective and power efficient silicon photonic components for high capacity routing applications. The project has focused on a hybrid integration technology allowing Si manufacturing with III-V material processing for the implementation of a wide range of optical functionalities, including high speed optical transmission, modulation and wavelength conversion, on the silicon-on-insulator substrate.
BOOM has invested on the micro-solder fabrication technique for the hybridization of active components on silicon boards. The Au-Sn bumping process has reached adequate level of optimization during the BOOMing years. A key-milestone success has been the flip-chip bonding of SOAs and EML transmitters on the SOI boards with placement accuracy down to submicron level enabling the fabrication of silicon-on-insulator hybrid components with good electrical/optical properties. This has been a major achievement since it proved that the current flip-chip assembly technology could certainly provide mounting capabilities well below the multi-mode fiber limit. Compared to other techniques, BOOM micro-soldering technology has been more flexible and compatible with advanced III-V processing steps.
BOOM has advanced the state-of-the-art in photonic wavelength conversion devices developing scalable all-optical wavelength converters (AOWCs) with record integrated line-rate performance. In contrary with silica-on-silicon demonstrations, BOOM converters have increased aggregate switching capacity by a factor of 4, assisting for first time data rates up to 160Gb/s. In terms of footprint, silicon wavelength converters have been more compact devices (10 times squeeze) due to their high refractive index material. With respect to energy consumption, BOOM devices consumed less power (by a factor of 7) compared to Mach-zehnder interferometric structures due to the utilization of only one active element for the wavelength conversion process.
The InP-photodetectors developed in BOOM have been in direct competition with Ge-detectors for integration with silicon waveguides. Their hybridization has been performed with the heterogeneous wafer-scale integration technique. A persistent difficulty with this approach has been the high series resistance and the non-uniformity BCB layer thickness limiting the high-speed optical transit time of the detectors. From a fabrication point of view, a key success has been an adaptation in the flow process mechanism in order to minimize contamination of the surface prior to metal deposition ensuring good metal/semiconductor contact. From the design point of view, a significant improvement has been performed in the III-V epitaxial growth so as the photodetector to be more transit time limited than RC limited. The new technological methodology has been proved reliable and fully extendable to other materials and other wavelength ranges.
As general conclusion, BOOM has offered mature technology setting the basis for large scale implementation of cost-effective and power-efficient silicon components. BOOM has faced difficulties but eventually succeeded in demonstrating reliable and state-of-the-art components. In our opinion, BOOM has been a highly successful project that turned silicon photonics into a stable and powerful integration platform.
Agile Photonic Integrated Systems-on-Chip enabling WDM Terabit Networks
[April 2008 – March 2011]
APACHE aimed to develop photonic integrated components capable of generating, regenerating and receiving signals of various modulation formats and rates involving amplitude- and differentially phase- encoded signals (i.e. OOK, DPSK and DQPSK) for high capacity agile WDM optical networks. Component fabrication within APACHE focused on the development of a hybrid integration technology platform for the integration of high performance monolithic active elements based on Indium Phosphide (InP) on low loss silica-on-silicon substrates, enabling the development of advanced photonic integrated circuits (PICs) with complex functionalities on chip.
More specifically, APACHE envisaged highly ambitious objectives that dealt with the design and fabrication of a) two types of transmitter arrays suitable for metro/core terabit network applications, b) a multi-format signal processing chip suitable for signal regeneration and wavelength conversion of different modulation formats and c) receiver arrays suitable for amplitude and phase encoded signals. The building blocks that were developed comprised arrays of: nested IQ Mach Zehnder Modulators (MZMs) and tunable distributed-feedback (DFB) laser arrays targeting up to 200 Gb/s throughput for single chips and terabit capacity (5x200Gb/s) for the array device, arrays of reflective electro-absorption modulators (REAMs) and arrays of reflective SOA-based lasers targeting 10x10Gb/s low cost metro applications, arrays of detectors with integrated delay interferometers for phase decoding on chip and SOA arrays embedded on complex Mach Zehnder Interferometer (MZI) structures for signal processing functionalities. The fabrication activities were supported by sophisticated simulation and software design tools that were developed within the project. Within APACHE, a full version of a software ‘design kit’ for photonic integration was demonstrated commercially and comprised the first design tool for the integration of optical circuits. Finally, the developed photonic devices have been successfully characterized and tested under laboratory and real network WDM transmission scenarios. Benchmarking of the APACHE devices against Ericsson transponders demonstrated that the APACHE technology would be an eligible solution for 100G systems in the next two or three years when their overall cost was expected to be further reduced.
The APACHE research outcomes and results have been presented in several International conferences, exhibition halls and variable types of audiences as well as in peer reviewed journals and magazines. A number of invited talks and paper contributions regarding the APACHE technology have been carried out. The exploitation of the APACHE technology within industry and commercial use was also one of the main targets of the project. The commercial version of the first software design kit platform was released within the duration of the project. Also, the consortium continuously pursued to advance the knowledge and experience gained within APACHE by promoting external contracts with industrial partners. In all, APACHE successfully completed most of its technical goals and promoted the dissemination and exploitation of results yielding a direct impact on the socio-economic and the societal position of the European Community.
Building the Future Optical Network in Europe
[January 2008 – December 2010]
The core activity of the BONE-project was the stimulation of intensified collaboration, exchange of researchers and integration of activities and know-how into and amongst partners. Through the establishment of Virtual Centres of Excellence, the BONE-project looks into the future and builds and supports the final “Network of the Future” through education & training, research tools & testlabs on new technologies & architectures. The leading-edge position of European Research in the field and, consequently, of European industry, could be threatened by returning to an uncoordinated and scattered approach to optical networking research. BONE consolidates the process, supported during FP6, of integration and reorganization of research efforts across European academic and industrial groups in FP7 through:
Building Virtual Centres of Excellence that cover specific issues in the field of Optical Networking that can serve to European industry with education & training, research tools & testlabs and pave the way to development of new technologies & architectures.
Reaching out, including and linking to research activities in national programmes, or programmes outside Europe.
Stimulating an intensified collaboration, exchange of researchers between the research groups involved and active in the field.
Disseminating the expertise and know-how of these European Research groups to a broader audience, both R&D oriented as well as industry- and decision maker oriented.
Cost-effective MULTI-WAVElength Laser System
[November 2005 – October 2007]
The MultiWave project has demonstrated a multi-wavelength platform capable of generating source signals with channel spacing in the range of 12.5G, 25G, 50G, 100G or higher on the ITU grid, and covering the S, C, and L band. Error-free operation of the modulated channels in the C-band was obtained with performance equal to or better than commercial DFB lasers. MultiWave has demonstrated a cost-effective platform for upgrading present and future broadband fiber optic links.
Optical Networks: Towards Bandwidth Manageability and Cost Efficiency
[March 2004 – February 2008]
The Network of Excellence (NoE) “e-Photon/ONe+: Towards Bandwidth Manageability and Cost Efficiency” covered the technical area of optical networking.
The project was funded for 24 months in FP6 Call 4 under strategic objective “Broadband for All”, with starting date March 1st, 2006, in temporal and technical continuation with a previous project called e-Photon/ONe funded in FP6 Call 1. Overall, the two phases of the NoE were funded for 4 years (plus a one-month extension).
The broad objectives of the e-Photon/ONe Network of Excellence (in its two phases) have been the following:
- Integrate and focus the rich know-how available in Europe on optical communications and networking (from optical technologies, to networking devices, to network architectures and protocols, to the new services fostered by photonic technologies), both in universities and in research centers of well-positioned telecom manufacturers and operators.
- Favor a coordination among the participants to reach a consensus on the engineering choices towards the deployment of optical networks, possibly providing inputs to standardization bodies and guidelines to operators.
- Provide guidelines for the design of an optical Internet backbone, metro, access and in-home infrastructure, supporting traffic engineering and quality of service management in an end-to-end perspective.
- Understand how the intrinsic characteristic of optical technologies can be exploited to provide large bandwidth together with acceptable levels of quality of service and protection/restoration inside and across network domains.
- Promote and organize integration activities aiming at establishing a good exchange of information, and long-term collaborations in terms of research, infrastructure sharing, education and training, among participating institutions.
- Promote and organize activities to disseminate knowledge on optical networks in the technical community and to the general public, through coordinated publications, technical events, and interactions with other consortia in the same technical area.
In addition to research and technical activities, e-Photon/ONe put a strong emphasis on dissemination activities, with the aim of converting the international reputation of individual partners into a quality label for the network. Specific dissemination goals were:
- Regularly organize technical schools on selected topics;
- Organize workshops with these schools where young researchers can present their research work;
- Establish regular links with, and provide active support to, major international conferences on optical networking and communications;
- Present and promote e-Photon/ONe within the international scientific community;
- Establish links with other EU-projects in the field, and with a number of industry associations or professional organizations;
- Favor technical interactions with excellent institutions outside Europe (USA, Japan, China, ecc.);
- Publication of joint technical papers;
- Active participation to editorial boards of optical networking journals (Elsevier Optical Switching and Networking, IEEE Transactions on Networking, etc.);
- Management of the e-Photon/ONe web site.
Finally, given the strong presence of universities in the project, a significant effort was devoted to teaching and training activities. Training activities must help improve the skills and knowledge of the future young workforce and indirectly help to establish a competitive and knowledge economy. e-Photon/ONe focused on organizing technical schools (mainly for PhD students), and on searching consensus in teaching programs. More specifically, e-Photon/ONe partners collaborated to define a syllabus for a master program in optical communications and networks, with collection and joint editing of teaching material (slides and course notes).
The management of e-Photon/ONe was implemented in a number of bodies and committees:
- Project Office and Project Co-ordinator at Politecnico di Torino
- General Assembly, composed by all NoE partners
- JPA Committee: main executive body of the network, responsible for the implementation of the Joint Program of Activities (JPA); it was articulated in four boards:
- Integrating Activities Board
- Joint Research Projects Board o Exchange and Mobility Board
- Dissemination and Training Board and two panels:
- Gender Issue Panel
- Innovation and IPR Panel
- Quality Assurance Committee (QAC): it comprised four experts external to the NoE, and provides content monitoring and quality control
- Local Administrators and JPA representatives for each partner
The follow-up project of ePhoton/ONe was the NoE BONE in FP7.
Multi – Functional In tegrated Arrays of Interferometric Switches
[September 2004 – August 2007]
The MUFINS project aimed to take the next logical step in the evolution of all-optical signal processing, to integrate multiple switching elements on a single chip, and to interconnect these integrated switching elements into functional logic modules with the aid of a external components. 2×2 Mach Zehnder Interferometers that operate as all-optical switches were fabricated as two and four element integrated arrays. These switches were used as the main building blocks for the development of a wide range of functionalsubsystems, such as Header Extraction, Half Adder, Full Adder, Time Slot Interchanger, Clock and Data Recovery, Data Vortex Switch, 4×4 Switching Matrix, all- optical 4-wavelength Burst Mode Receiver, 40 Gb/s all-optical Burst Mode Receiver.
All-optical LAbel-SwApping employing optical logic G ates in NEtwork nodes
[January 2004 – December 2006]
PCRL participated in the LASAGNE project that aimed at studying, proposing and validating the use of all-optical logic gates and optical flip-flops based on commercially-available technologies to implement the required functionalities at the metro network nodes in All-optical label swapping (AOLS) networks. The optical gates were implemented using the same key building block: SOA-based Mach-Zehnder interferometers (MZIs). A functional photonic router prototype incorporating all-optical label swapping and wavelength conversion was integrated using optical logic gates and optical flip-flops. This photonic router was designed to be modular, scalable, and with potential for system integration.
Digital Optical Logic Modules
[November 1998 – September 2002]
PCRL coordinated project DO_ALL, a project within the ESPRIT frame-programme. The aim of project DO_ALL was to research in a systematic way the state-of-the-art in high-speed all-optical logic and to develop novel signal processing concepts and technologies. In this respect, DO_ALL has defined, designed, and developed the necessary set of devices and modules required for the construction of optical logic circuits and has applied them into application experiments of nontrivial functionality to qualify their performance and limitations. Within this frame, the applications that have been explored were (1) the demonstration of all-optical bit-error-rate (BER) measurements capability and (2) the demonstration of an optically addressable exchange–bypass switch using all-optical techniques. The first application was selected so as to investigate whether it is possible to build a complex optical circuit consisting of several optical logic modules that would challenge in performance the corresponding electronic designs. The second application was chosen so as to demonstrate that the logical functionality of optical circuits is advantageous since in this instance one optical gate can replace several electronic gates